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| Product Description Sirenza Microdevices' SLD-1000 is a robust 4 Watt high performance LDMOS transistor die, designed for operation from 10 to 2700MHz. It is an excellent solution for applications requiring high linearity and efficiency. The SLD-1000 is typically used as a driver or output stage for power amplifier, or transmitter applications. These robust power transistors are fabricated using Sirenza's high performance XEMOS IITM process. SLD-1000 4 Watt Discrete LDMOS FET -Bare Die Functional Schematic Diagram ESD Protection * * * * * * * Product Features 4 Watt Output P1dB Single Polarity Operation 19dB Gain at 900 MHz XeMOS IITM LDMOS Integrated ESD Protection, Class 1B Aluminum Topside Metallization Gold Backside Metallization Gate Manifold Drain Manifold Source - Backside Contact RF Specifications Symbol Frequency Gain Efficiency Linearity RTH Parameter Frequency of Operation 3.5 Watts CW, 900 MHz Drain Efficiency at 3.5 Watts CW, 900 MHz * * * * * Applications Base Station PA Driver Repeaters Military Communications RFID GSM, CDMA, Edge, WDCDMA Unit MHz dB % dBc Watts C/W Min 10 Typ 19 43 -30 4 11 Max 2700 - 3rd Order IMD at 3.5 Watts PEP (Two Tone) 900 MHz 1dB Compression (P1dB) 900 MHz Thermal Resistance (Junction-to-Case, mounted in package) Test Conditions: Mounted in ceramic package and tested in SirenzaT Evaluation Board VDS = 28.0V, IDQ = 30mA, TMounting Surface = 25C DC Specifications Symbol gm VGS Threshold VDS Breakdown Ciss Crss Coss RDSon Parameter Forward Transconductance @ 30mA IDS IDS=3mA 1mA IDS Current Input Capacitance (Gate to Source) VGS=0V, VDS=28V Reverse Capacitance (Gate to Drain) VGS=0V, VDS=28V Output Capacitance (Drain to Source) VGS=0V, VDS=28V Drain to Source Resistance, VGS=10V VDS=250mV Unit mA / V Volts Volts pF pF pF 3.0 65 Min Typical 150 4.2 70 5.2 0.2 3.2 3.0 3.5 5.0 Max The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-104291 Rev C SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die Quality Specifications Parameter ESD Rating MTTF Description Human Body Model 200oC Channel Unit Volts Hours Typical 750 1.2 X 106 Contact Description Pad # 1 2 3 Function Gate Drain Source Description Aluminum metallized manifold MOSFET Gate with ESD protection structure. (Topside contact) Aluminum metallized manifold MOSFET Drain. (Topside contact) Chrome Gold metallized MOSFET Source contact. Appropriate electrical, mechanical and thermal connection required for proper operation. (Backside contact) Pad Diagram ESD Protection Note 1: Gate voltage must be applied to to the device concurrently or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages should never be applied to the transistor unless it is properly terminated on both input and output. Note 2: The required VGS corresponding to a specific IDQ will vary from device to device due to the normal die-to-die variation in threshold voltage with LDMOS transistors. Note 3: The threshold voltage (VGSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza application notes AN-067 LDMOS Bias Temperature Compensation. Pad #3 Backside Source = Ground Pad #1 Gate Manifold Pad #2 Drain Manifold Absolute Maximum Ratings Parameters Drain Voltage (VDS ) Gate Voltage (VGS), VDS =0 RF Input Power Load Impedance for Continuous Operation Without Damage Output Device Channel Temperature Storage Temperature Range Value 35 20 +30 10:1 +200 -40 to +150 Unit Volts Volts dBm VSWR C C Operation of this device beyond any one of these limits may cause permanent damage. For reliable continuous operation see typical setup values specified in the table on page one. Caution: ESD Sensitive Appropriate precaution in handling, packaging and testing devices must be observed. 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 2 http://www.sirenza.com EDS-104291 Rev C SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die Impedance Data Frequency (MHz) 880 960 1840 1960 2140 Zsource 2.7 + j 13.1 1.9 + j 10.6 1.7 + j 3.4 1.3 + j 2.0 1.2 + j 0.7 Zload 12.5 + j 22.5 11.8 + j 18.3 1.0 + j 4.7 1.2 + j 5.7 1.7 + j 6.4 De-embedding Information Description Number of Bond Wires Length of Bond Wires Height of Bond Wires Pitch of Bond Wires Bond Wire Diameter Gate 2 0.040 0.006 0.005 0.002 Drain 3 0.040 0.006 0.005 0.002 Impedances Referenced to Wirebond/PCB Interface. All Dimensions in Inches. Wirebond Heights Referenced to Top Surface of Die. Device under test Input Matching Network Z source Output Matching Network Z load Zsource and Zload are the optimal impedances presented to the SLD-1000 when operating at 28V, Idq=30mA, Pout=3.5 W PEP. 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 3 http://www.sirenza.com EDS-104291 Rev C SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die Typical Performance Curves for packaged die tested in SLD-1083CZ 900 MHz Application Circuit CW Gain, Efficiency, IRL vs Frequency Vdd=28V, Idq=50mA, Pout=3W 50 45 40 Gain (dB), Efficiency (%) 35 30 25 20 15 10 5 0 900 0 24 CW Gain, Efficiency vs Pout Vdd=28V, Idq=50mA, Freq=915 MHz 60 -4 23 50 IRL -12 21 30 20 20 Gain 19 -16 Efficiency 10 905 910 915 920 -20 925 18 0 1 2 Pout (W) 3 4 5 0 Frequency (MHz) 60 2 Tone Gain, Efficiency, Linearity and IRL vs Frequency Vdd=28V, Idq=50mA, Pout=3W PEP, Delta F=1 MHz Gain IM3 IM7 Efficiency IM5 IRL 0 50 45 2 Tone Gain, Efficiency, Linearity vs Pout Vdd=28V, Idq=50mA, Freq=915 MHz, Delta F=1 MHz -20 -25 -30 -35 IMD (dBc) -40 -45 -50 -55 50 Gain (dB), Efficiency (%) -10 Gain (dB), Efficiency (%) 40 40 -20 IMD(dBc), IRL (dB) 35 30 25 20 15 10 5 30 -30 20 -40 10 -50 Gain IM3 IM7 0 1 2 3 Pout (W PEP) Efficiency IM5 -60 -65 -70 0 900 905 910 915 920 Frequency (MHz) -60 925 0 4 5 6 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 4 http://www.sirenza.com EDS-104291 Rev C Efficiency (%) Gain Efficiency Input Return Loss (dB) 22 Gain (dB) 40 -8 SLD-1000 10-2700 MHz 4 Watt LDMOS FET - Bare Die Die Map Dimensions Inches [mm] 0.030 [0.76] GATE 0.045 [1.14] DRAIN SOURCE - BACKSIDE CONTACT - NOT SHOWN DIE THICKNESS - 0.004 [0.10] AuSi, AuSn, or AuGe eutectic die attach is recommended. AlSi bond wires are recommended. Part Number Ordering Information Part Number SLD-1000 Gel Pack 100 pcs. per pack Die are screened prior to dicing to DC parameters and are shipped per Sirenza application note AN-039 Visual Criteria of Unpackaged Die. 303 S. Technology Court Broomfield, CO 80021 Phone: (800) SMI-MMIC 5 http://www.sirenza.com EDS-104291 Rev C |
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